Signal via positioning in a multi-layer circuit board using a genetic via placement solver

ABSTRACT

One aspect includes identifying via groups that each includes a ratio of a plurality of signal vias to one ground via based on a design file defining a layout of a multi-layer circuit board. A genetic via placement solver iteratively evaluates potential placement solutions that adjust a placement of one or more of the signal vias until at least one solution is identified that meets one or more placement criteria of the signal vias. The genetic via placement solver performs a mutation and recombination of one or more solutions that do not meet the one or more placement criteria and re-evaluates the one or more solutions that do not meet the one or more placement criteria. The design file is modified to include at least one shifted signal via position based on identifying the at least one solution that meets the one or more placement criteria.

DOMESITIC PRIORITY

This application is a continuation of U.S. patent application Ser. No.15/139,653, filed Apr. 27, 2016, the disclosure of which is incorporatedby reference herein in its entirety.

BACKGROUND

The present application relates generally to circuit boardmanufacturing. More specifically, the present application is directed tosignal via positioning in a multi-layer circuit board.

Printed circuit boards (“PCB”) are generally fabricated from a pluralityof laminated layers. Each of the layers typically includes a corefabricated from an insulating material, such as FR-4, epoxy glass,polyester or synthetic resin bonded paper, for example. Typically, acopper layer is bonded to one or both sides of the core. Circuits or“traces” are formed on the copper by applying a mask and removingunneeded copper. The individual layers are then laminated together toform the PCB.

Energy is typically transferred between layers of the PCB using powervias, signal vias, and ground vias. Signal vias are typically installedthrough all layers of a PCB even though the signal vias may only form anelectrical connection between two of the layers. A portion of a signalvia that extends through layers of the PCB beyond the points ofelectrical connection is referred to as a “stub”. For high-speedsignals, if stubs are not removed, sharp resonances can appear as aninsertion loss, particularly in a differential signal pair.

Stubs can be removed by back-drilling the unused portion of the signalvias out of the PCB during manufacturing. However, the ability toback-drill signal vias is constrained by a minimum drilling distancedefined between the signal vias. The potential for damaging the PCBincreases considerably if the minimum drilling distance is violated.This minimum drilling distance effectively constrains the minimum pitch(i.e., center-to-center distance) that can be supported, and thus,limits signal density under a chip or module.

SUMMARY

Embodiments include a method of signal via positioning. The methodincludes identifying, by a via placement tool executing on a processorof a circuit design system, a plurality of via groups each including aratio of a plurality of signal vias to one ground via based on a designfile defining a layout of a multi-layer circuit board. A genetic viaplacement solver iteratively evaluates a plurality of potentialplacement solutions that adjust a placement of one or more of the signalvias until at least one solution is identified that meets one or moreplacement criteria of the signal vias. The genetic via placement solverperforms a mutation and recombination of one or more solutions that donot meet the one or more placement criteria and re-evaluates the one ormore solutions that do not meet the one or more placement criteria. Thedesign file is modified to include at least one shifted signal viaposition based on identifying the at least one solution that meets theone or more placement criteria.

Embodiments also include a system having a design file defining a layoutof a multi-layer circuit board including a plurality of via groups eachincluding a ratio of a plurality of signal vias to one ground via. Thesystem also includes a processor that is configured to iterativelyevaluate a plurality of potential placement solutions that adjust aplacement of one or more of the signal vias until at least one solutionis identified that meets one or more placement criteria of the signalvias. The system performs a mutation and recombination of one or moresolutions that do not meet the one or more placement criteria andre-evaluates the one or more solutions that do not meet the one or moreplacement criteria. The design file is modified to include at least oneshifted signal via position based on identifying the at least onesolution that meets the one or more placement criteria.

Embodiments also include a computer program product. The computerprogram product includes a computer readable storage medium havingcomputer readable program code embodied therewith. The programinstructions are executable by a processor to perform a method thatincludes identifying a plurality of via groups each including a ratio ofa plurality of signal vias to one ground via based on a design filedefining a layout of a multi-layer circuit board. Potential placementsolutions are iteratively evaluated to adjust a placement of one or moreof the signal vias until at least one solution is identified that meetsone or more placement criteria of the signal vias. Mutation andrecombination of one or more solutions that do not meet the one or moreplacement criteria are performed. Solutions that do not meet the one ormore placement criteria are re-evaluated. The design file is modified toinclude at least one shifted signal via position based on identifyingthe at least one solution that meets one or more placement criteria.

Additional features and advantages are realized through the techniquesof the present invention. Other embodiments and aspects of the inventionare described in detail herein and are considered a part of the claimedinvention. For a better understanding of the invention with theadvantages and the features, refer to the description and to thedrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter which is regarded as the invention is particularlypointed out and distinctly claimed in the claims at the conclusion ofthe specification. The forgoing and other features, and advantages ofthe invention are apparent from the following detailed description takenin conjunction with the accompanying drawings in which:

FIG. 1 is an exemplary diagram of a multi-layer circuit boardmanufactured according to aspects of exemplary embodiments;

FIG. 2 depicts an example of a genetic algorithm process applied by avia placement tool according to aspects of exemplary embodiments;

FIG. 3 depicts an example of signal via placement shifting with a 4:1signal-to-ground ratio in a multi-layer circuit board according to anembodiment;

FIG. 4 depicts an example of signal via and ground via placementshifting with a 4:1 signal-to-ground ratio in a multi-layer circuitboard according to an embodiment;

FIG. 5 depicts another example of signal via and ground via placementshifting with a 4:1 signal-to-ground ratio in a multi-layer circuitboard according to an embodiment;

FIG. 6 depicts an example of signal via and ground via placementshifting using elongated pads with a 4:1 signal-to-ground ratio in amulti-layer circuit board according to an embodiment;

FIG. 7 depicts an example of selectively shifting a subset of signalvias with a 4:1 signal-to-ground ratio in a multi-layer circuit boardaccording to an embodiment;

FIG. 8 depicts another example of selectively shifting a subset ofsignal vias with a 4:1 signal-to-ground ratio in a multi-layer circuitboard according to an embodiment;

FIG. 9 depicts another example of signal via and ground via placementshifting with a 4:1 signal-to-ground ratio in a multi-layer circuitboard according to an embodiment;

FIG. 10 illustrates a system for signal via positioning in a multi-layercircuit board in accordance with an exemplary embodiment; and

FIG. 11 illustrates a process of positioning signal vias in amulti-layer circuit board in accordance with an exemplary embodiment.

DETAILED DESCRIPTION

Exemplary embodiments include systems, methods and computer programproducts for positioning of signal vias in a multi-layer circuit board.Signal vias may be grouped, for instance, to support differentialsignaling through the multi-layer circuit board. Each group of signalvias may also be associated with or include a ground via. Signal pathsfor higher speed signals that include signal vias may be sensitive toadditional “stub” material that extends beyond a signal path to thebottom of a multi-layer circuit board, also referred to as printedcircuit board (PCB). As depicted in FIG. 1, a system 100 can include amulti-layer circuit board 101. In the example of FIG. 1, the multi-layercircuit board 101 includes N-layers 102, where “N” is an arbitrarynumber, such as twenty. Layer 102A is an uppermost layer that interfacessignal vias 104 and ground vias 106 to bottom surface metal 108 (e.g.,conductive contacts) of a module 110. The module 110 can be a chip orany type of package that can be coupled to the multi-layer circuit board101 to form the system 100.

Various paths 112 may be routed to different layers 102 of themulti-layer circuit board 101. For example, signal path 112A, signalpath 112B, signal path 112C and signal path 112D may be routed in layer102D. Layers 102B and 102C may be reserved for other signal paths (notdepicted), and ground path 112E may be routed in layer 102E. As depictedin FIG. 1, signal via 104A may extend between layer 102A and layer 102Nof the multi-layer circuit board 101; however, the portion of signal via104A between layers 102E and 102N forms a stub 114A since it extendsbelow the signal path 112A. Electrical continuity is only needed betweenbottom surface metal 108A and the portion of signal via 104A thatextends from layer 102A to layer 102D to reach the signal path 112A.Signal via 104B may extend between layer 102A and layer 102N of themulti-layer circuit board 101, and the portion of signal via 104Bbetween layers 102E and 102N forms a stub 114B since it extends belowthe signal path 112B. Electrical continuity is only needed betweenbottom surface metal 108B and the portion of signal via 104B thatextends from layer 102A to layer 102D to reach the signal path 112B.Similarly, signal vias 104C and 104D may extend between layer 102A andlayer 102N of the multi-layer circuit board 101, and the portion ofsignal vias 104C and 104D between layers 102E and 102N forms stubs 114Cand 114D respectively. Ground via 106 also extends from layer 102A tolayer 102N. Although the ground via 106 is only needed between layers102A and 102E for bottom surface metal 108E in the example of FIG. 1,there is no detrimental effect to signal quality by leaving the portionof ground via 106 intact between layers 102E and 102N. By back-drillingsignal vias 104A-104D from layer 102N up to layer 102E, resonanceeffects can be reduced when stubs 114A-114D are removed. Additionalsignal vias may also be included between layers 102A-102N that do notrequire back-drilling due to a lower frequency of operation.

The center-to-center distances between a neighboring pair of bottomsurface metal 108A and 108B (as well as bottom surface metal 108B to108C and 108C to 108D) are referred to as the bottom surface metalpitch. The center-to-center distance between a neighboring pair of thesignal vias 104A and 104B (as well as signal vias 104B to 104C and 104Cto 104D) is referred to as the signal via pitch. A minimum value of thesignal via pitch is limited due to manufacturing constraints as a targetminimum drilling distance to allow back-drilling of the neighboring pairof the signal vias 104. Embodiments allow the bottom surface metal pitchto be designed with a value that is less than the target minimumdrilling distance. In contrast, contemporary art solutions typicallyrequire that the bottom surface metal pitch be greater than the targetminimum drilling distance.

FIG. 2 depicts an example of a genetic placement algorithm process 200applied by a via placement tool (e.g., via placement tool 1070 of FIG.10) according to an embodiment. The genetic placement algorithm process200 includes a genetic via placement solver 202 that compiles andanalyzes 204 a problem specification 206 to support generation of randomsolutions 208, evaluation of solutions 210 and performance of mutationand re-combinations 212. Evaluation of solutions 210 is performed withrespect to a fitness function 214, where resulting solutions can beranked 216 and compared to placement criteria 218 to determine whether asolution 220 meets the placement criteria or if performance of mutationand re-combinations 212 is needed to continue with the evaluation ofsolutions 210. For example, the solution 220 can include radial andangular shifts to existing positions of vias, such as signal vias104A-104D and ground via 106 of FIG. 1.

The problem specification 206 can be defined according to equation 1 asδ{right arrow over (r)}_(n)=ρ_(n)∠Ø_(n) for nε

. . . N for shifts in N unique via positions in the configuration. Therecan be fewer unique positions N than vias defined. For instance, theexample of FIG. 3 illustrates a condition of N=4 with 21 shifted signalvias. Equation 2 defines via positions to test as: {right arrow over(r_(l))}={right arrow over (r^(t) _(l)

)}+δ{right arrow over (r)}_(n). The fitness function 214 can be definedaccording to equation 3: d_(k)=min_(∀i≠j)|{right arrow over(r_(l))}−{right arrow over (r_(j))}|, where {right arrow over (r_(l))}and {right arrow over (r_(j) )} are back-drilled via positions withshifts applied according to a shift constraint. As one example, theshift constraint can be to set the fitness=d_(k) if d_(k)

≧0.5 mm; otherwise the fitness can be set to

$- {\frac{50}{{\min\left\{ d_{j} \right\}} + {{near}\mspace{14mu}{zero}\mspace{14mu}{value}}}.}$The near zero value prevents a divide by zero condition. The values of0.5 mm and 50 can be adjusted depending upon the desired via positionshift limitations. The genetic via placement solver 202 iterates until asolution 220 meeting the placement criteria 218 is identified. Solutionscan include different radius values (mm) and angles (degrees) for eachsignal via 104A-104D in a 4:1 signal via to ground via configurationwith instances of the solution repeated for the multi-layer circuitboard 101 to support module 110 of FIG. 1, for instance. Manualadjustments to the solution 220 can be made if desired, or the problemspecification 206 can be further refined to enhance alignment of aregular pattern that meets the minimum separation requirements. Forinstance, as one example that maintains a minimum separation of 1.0806mm (which is greater than a 1.06 mm restriction), signal via 104A can beshifted 0.165 mm at an angle of 45 degrees, signal via 104B can beshifted 0.055 mm at an angle of 45 degrees, signal via 104C can beshifted 0.055 mm at an angle of −135 degrees, and signal via 104D can beshifted 0.165 mm at an angle of −135 degrees.

FIG. 3 depicts an example of signal via placement shifting 300 with a4:1 signal-to-ground ratio in a multi-layer circuit board according toan embodiment. A portion of a repeating pattern of via groups 302 eachincluding four signal vias 304A-304D and a ground via 306 (i.e., a 4:1signal via to ground via ratio) is depicted in FIG. 3, with onlypositions of the signal vias 304A-304D shifting. Signal via 304A istypically centered under pad 308A; however, upon executing the geneticplacement algorithm process 200 of FIG. 2, a shifted signal via position310A is determined with respect to the signal via 304A that meetsplacement constraints (e.g., placement criteria 218 of FIG. 2).Similarly, signal vias 304B, 304C, and 304D are moved off center frompads 308B, 308C, and 308D to shifted signal via positions 310B, 310C,and 310D respectively. The magnitude of position shifting can vary forone or more of the shifted signal via positions 310A-310D. When there issubstantial overlap with the pads 308A-308D and the shifted signal viapositions 310A-310D respectively, no additional alterations may beneeded to establish electrical conductivity between the pads 308A-308Dand the signal vias 304A-304D at the shifted signal via positions310A-310D. Close alignment enables a via-in-pad structure that can beuseful for land grid arrays and/or soldered sockets, for example. Arelatively small shift in position can be sufficient to meet aback-drilling minimum pitch threshold. For instance, maintaining aminimum separation between the signal vias 304A-304D at the shiftedsignal via positions 310A-310D may result in a gain of 81 μm over atypical 1 mm pitch (i.e., a pitch of 1.0806 mm), which exceeds theback-drilling minimum pitch threshold of 1.06 mm.

The ground vias 306 and pads 308A-308D maintain a substantially uniformdistribution for the multi-layer circuit board 101 of FIG. 1. Thesubstantially uniform distribution need not be a precisely uniformdistribution and can vary within a manufacturing tolerance. As part of amanufacturing process, a via placement tool (e.g., via placement tool1070 of FIG. 10) can be executed on a processor to determine and modifythe positioning of signal vias 304A-304D as embodiments of the signalvias 104 in the multi-layer circuit board 101 of FIG. 1. Initially, inthe substantially uniform distribution, the signal vias 304A-304D andground vias 306 can be distributed substantially equally to align withthe bottom surface metal pitch of module 110 of FIG. 1. In the exampleof FIG. 3, vias 304 and 306 are grouped in a configuration of foursignal vias 304A-304D to one ground via 306. There can be manyneighboring groups of signal vias 304A-304D to which embodiments areapplied.

Since ground vias 306 do not need to be back-drilled, signal vias304A-304D can be moved closer to ground vias 306 as long as a sufficientdistance is maintained to prevent a short circuit to ground. Bypositioning the signal vias 304A-304D closer to ground vias 306, thetarget minimum drilling distance can be maintained as the signal viapitch is increased to be greater than the bottom surface metal pitch bymoving the signal vias 304A-304D much closer to ground vias 306.Conversely, the distance between a number of the signal vias 304A-304Dand the ground vias 306 is reduced to be less than the bottom surfacemetal pitch.

FIG. 4 depicts an example of signal via and ground via placementshifting 400 with a 4:1 signal-to-ground ratio in a repeating pattern ofvia groups 402 and having a larger shift as compared to the shifting ofFIG. 3. In order to reposition signal vias 404A-404D without requiring ashift or size change to the bottom surface metal 108 on module 110 ofFIG. 1, extensions to pads 408A, 408B, 408C, and 408D can be added tothe uppermost layer 102A of the multi-layer circuit board 101 of FIG. 1to align with bottom surface metal 108 of module 110 to be coupled tothe multi-layer circuit board 101 as depicted in FIG. 4. Pad extensions407A, 407B, 407C, and 407D may be in the form of “dog bones” thatprovide a conductive path on the uppermost layer 102A between shiftedsignal via positions 410A, 410B, 410C and 410D after the signal vias404A-404D are shifted from the locations of pads 408A-408D. Thus, evenif the signal vias 404A-404D do not directly align with bottom surfacemetal 108 of FIG. 1 after positioning, the pad extensions 407A-407D canestablish electrical continuity between the signal vias 404A-404D andrespective bottom surface metal 108 of FIG. 1.

In FIG. 4, each of the ground vias 406 is also shifted using padextension 411 from the location of pad 412 to a shifted ground viaposition 414. In some embodiments, the size of pad extensions 407A-407Dand 411 is the same, although the orientation and placement location canvary as determined by a via placement tool (e.g., via placement tool1070 of FIG. 10) using the genetic placement algorithm process 200 ofFIG. 2. Thus, although the pads 408A-408D and 412 have a substantiallyuniform distribution, the pad extensions 407A-407D and 411 enable anumber of non-uniform placement options for signal vias 404A-404D andground vias 406 such that sufficient back-drilling margin exists betweenthe signal vias 404A-404D.

FIG. 5 depicts another example of signal via and ground via placementshifting 500 with a 4:1 signal-to-ground ratio in a repeating pattern ofvia groups 502 and having a smaller shift as compared to the shifting ofFIG. 4. Pad extensions 507 are shorter than pad extensions 407A-407D ofFIG. 4 such that signal vias 504 at shifted signal via positions 510 arein closer physical proximity to pads 508 as compared to the example ofFIG. 4. Similarly, ground vias 506 use a pad extension 511 from thelocation of pad 512 to a shifted ground via position 514 that is shorterrelative to the pad extension 411 of FIG. 4.

FIG. 6 depicts an example of signal via and ground via placementshifting 600 using elongated pads with a 4:1 signal-to-ground ratio in arepeating pattern of via groups 602. The signal vias 604 areelectrically coupled to elongated pads 608 rather than substantiallycircular shaped pads. Similarly, ground vias 606 can each beelectrically coupled to an elongated pad 612. The use of elongated pads608 and 612 may be preferable depending on the connecting surfaceorientation, for instance, land grid array pin orientation.

Further separation between back-drilled signal vias can be achieved byfurther differentiating signal vias between back-drilled andnon-back-drilled signal vias as illustrated in FIGS. 7-9. FIG. 7 depictsan example of selectively shifting 700 a subset of signal vias with a4:1 signal-to-ground ratio in a repeating pattern of via groups 702.Non-back-drilled signal vias 705 and ground vias 706 are not shifted,while signal vias 704 are shifted. The non-back-drilled signal vias 705can be configured to carry lower operating frequencies as compared tosignal vias 704 (e.g., power vias and lower speed signaling vias).Similarly, FIG. 8 depicts an example of selectively shifting 800 asubset of signal vias with a 4:1 signal-to-ground ratio in a repeatingpattern of via groups 802. Non-back-drilled signal vias 805 and groundvias 806 are not shifted, while signal vias 804 are shifted. A largermagnitude of shifting occurs with respect to FIG. 8 as compared to FIG.7 by setting a different radial shift limit in the genetic placementalgorithm process 200 of FIG. 2 for the shifting 800 as compared to theshifting 700. For instance, with respect to FIG. 7, signal vias 704 mayachieve a minimum separation of 1.2552 mm with a radial shift limit of0.5 mm, while signal vias 804 may achieve a minimum separation of 1.399mm with a radial shift limit of 0.75 mm in designs with a 1.06 mmrestriction. The solution can be scaled to high or lowerpitch/separation limits. For instance, when scaled to a 0.8 mm pitchdesign, a separation of 1.119 mm may be achieved according toembodiments. In the example of FIG. 9, shifting 900 of various amountsin a repeating pattern of via groups 902 can be performed for signalvias 904, non-back-drilled signal vias 905, and ground vias 906.

FIG. 10 illustrates a block diagram of a computer system 1000 for use insignal via positioning in a multi-layer circuit board according to someembodiments. The systems and methods described herein may be implementedin hardware, software (e.g., firmware), or a combination thereof. Insome embodiments, the methods described may be implemented, at least inpart, in hardware and may be part of the microprocessor of a computersystem 1000, such as a personal computer, workstation, minicomputer,tablet computer, mobile device, or mainframe computer. The computersystem 1000 is also referred to as circuit design system 1000 and can beequipped with additional software and hardware to support circuitdesign, layout, and manufacturing of a multi-layer printed circuitboard.

In some embodiments, as shown in FIG. 10, the computer system 1000includes a processor 1005, physical memory 1010 coupled to a memorycontroller 1015, and one or more input devices 1045 and/or outputdevices 1040, such as peripherals, that are communicatively coupledpower via a local I/O controller 1035. These devices 1040 and 1045 mayinclude, for example, a printer, a scanner, a microphone, and the like.Input devices such as a conventional keyboard 1050 and mouse 1055 may becoupled to the I/O controller 1035. The I/O controller 1035 may be, forexample, one or more buses or other wired or wireless connections, asare known in the art. The I/O controller 1035 may have additionalelements, which are omitted for simplicity, such as controllers, buffers(caches), drivers, repeaters, and receivers, to enable communications.

The I/O devices 1040, 1045 may further include devices that communicateboth inputs and outputs, for instance disk and tape storage, a networkinterface card (MC) or modulator/demodulator (for accessing other files,devices, systems, or a network), a radio frequency (RF) or othertransceiver, a telephonic interface, a bridge, a router, and the like.

The processor 1005 is a hardware device for executing hardwareinstructions or software, particularly those stored in the physicalmemory 1010. The processor 1005 may be a custom made or commerciallyavailable processor, a central processing unit (CPU), an auxiliaryprocessor among several processors associated with the computer system1000, a semiconductor based microprocessor (in the form of a microchipor chip set), a macroprocessor, or other device for executinginstructions.

The memory 1010 may include one or combinations of volatile memoryelements (e.g., random access memory, RAM, such as DRAM, SRAM, SDRAM,etc.) and nonvolatile memory elements (e.g., ROM, erasable programmableread only memory (EPROM), electronically erasable programmable read onlymemory (EEPROM), programmable read only memory (PROM), tape, compactdisc read only memory (CD-ROM), disk, diskette, cartridge, cassette orthe like, etc.). Moreover, the memory 1010 may incorporate electronic,magnetic, optical, or other types of storage media. Note that the memory1010 may have a distributed architecture, where various components aresituated remote from one another but may be accessed by the processor1005.

The instructions in memory 1010 may include one or more separateprograms, each of which comprises an ordered listing of executableinstructions for implementing logical functions. In the example of FIG.10, the instructions in the memory 1010 include a suitable operatingsystem (OS) 1011. The operating system 1011 essentially may control theexecution of other computer programs and provides scheduling,input-output control, file and data management, memory management, andcommunication control and related services.

Additional data, including, for example, instructions for the processor1005 or other retrievable information, may be stored in storage 1020,which may be a storage device such as a hard disk drive or solid statedrive.

The computer system 1000 may further include a display controller 1025coupled to a display 1030. In some embodiments, the computer system 1000may further include a network interface 1060 for coupling to a network1065.

Systems and methods according to this disclosure may be embodied, inwhole or in part, in computer program products or in computer systems1000, such as that illustrated in FIG. 10. For example, a via placementtool 1070 can access a design file 1075 to determine a layout definitionof a multi-layer circuit board and transform the layout definition ofthe multi-layer circuit board according to the methods described hereinfor signal via positioning. The via placement tool 1070 may be comprisedof program instructions executable by the processor 1005. The viaplacement tool 1070 can be stored in a computer readable storage mediumsuch as the memory 1010 and/or storage 1020. Similarly, the design file1075 can be stored in a computer readable storage medium such as thememory 1010 and/or storage 1020. The via placement tool 1070 and/ordesign file 1075 may be received over the network 1065, and updates tothe design file 1075 can be transmitted over the network 1065 to supportother circuit board manufacturing operations. Although only a single viaplacement tool 1070 and design file 1075 are depicted in FIG. 10, itwill be understood that the via placement tool 1070 and/or design file1075 can be further subdivided, distributed, or incorporated as part ofanother application, file system, or data structure.

FIG. 11 illustrates a flow diagram of a method 1100 for signal viapositioning in a multi-layer circuit board in accordance with anexemplary embodiment. The method 1100 can be performed by the viaplacement tool 1070 executing on the processor 1005 of a circuit designsystem 1000 of FIG. 10 and is further described in reference to FIGS.1-10 for purposes of explanation. However, the method 1100 of FIG. 11can be implemented on systems with alternate configurations and elementsbeyond those depicted in the examples of FIGS. 1-10. The design file1075 is readable by manufacturing equipment to produce a tangiblerealization of the system 100 of FIG. 1 that complies with theconstraints and conditions as previously described.

At block 1102, the via placement tool 1070 executing on processor 1005of circuit design system 1000 identifies a plurality of via groups(e.g., groups 302) each including a ratio of a plurality of signal vias(e.g., signal vias 304A-304D) to one ground via (e.g., ground via 306)based on a design file 1075 defining a layout of the multi-layer circuitboard 101.

At block 1104, genetic via placement solver 202 iteratively evaluates aplurality of potential placement solutions that adjust a placement ofone or more of the signal vias (e.g., signal vias 304A-304D) until atleast one solution is identified that meets one or more placementcriteria 218 of the signal vias (e.g., signal vias 304A-304D).Evaluation of the potential placement solutions can be performed withrespect to a fitness function 214 that compares back-drilled viapositions with shifts applied according to a shift constraint. Thepotential placement solutions can include a plurality of differentradius values and angles to shift one or more of the signal vias (e.g.,to shifted signal via position 310A-310D). The one or more placementcriteria 218 can define a minimum separation between the signal vias(e.g., signal vias 304A-304D) subject to back-drilling. The potentialplacement solutions may include shifting one or more of the signal vias(e.g., signal vias 304A-304D) closer to the ground via (e.g., ground via306) in a same group or a different group such that a distance betweenthe at least one shifted signal via position and the ground via is lessthan the minimum separation between the signal vias (e.g., signal vias304A-304D) subject to back-drilling. The potential placement solutionscan include shifting one or more of the signal vias (e.g., signal vias704) closer to a non-back-drilled signal via (e.g., non-back-drilledsignal vias 705) such that a distance between the at least one shiftedsignal via position and the non-back-drilled signal via is less than theminimum separation between the signal vias subject to back-drilling.

At block 1106, genetic via placement solver 202 performs a mutation andrecombination of one or more solutions that do not meet the one or moreplacement criteria 218 and re-evaluates the one or more solutions thatdo not meet the one or more placement criteria 218.

At block 1108, the design file 1075 is modified to include at least oneshifted signal via position (e.g., shifted signal via position310A-310D) based on identifying the at least one solution 220 that meetsone or more placement criteria 218. The design file 1075 may also bemodified to add one or more pad extensions (e.g., pad extensions407A-407D and 411) to an uppermost layer 102A of the multi-layer circuitboard 101 to align with bottom surface metal 108 of module 110 to becoupled to the multi-layer circuit board 101. Each of the one or morepad extensions can establish an electrical connection with one of thesignal vias after the positioning. In some embodiments, an elongated pad(e.g., elongated pads 608 and 612) is coupled to the one or more padextensions to align with bottom surface metal of the module 110.

Technical effects and benefits include modifying a design layout of amulti-layer circuit board such that signal vias in a 4:1 signal toground via ratio configuration are separated to meet or exceed targetminimum drilling distance defined by manufacturing constraints whilemaintaining the same bottom surface metal pitch under modules coupled tothe multi-layer circuit board. This enables sufficient separation toperform back-drilling of the signal vias without compromising electricalor mechanical characteristics of the multi-layer circuit board.Alteration of the uppermost layer of the multi-layer circuit board canbe performed to align with bottom surface metal of a module to becoupled to the multi-layer circuit board.

It should be noted that the flowchart and block diagrams in the figuresillustrate the architecture, functionality, and operation of possibleimplementations of systems, apparatuses, methods and computer programproducts according to various embodiments of the invention. In thisregard, each block in the flowchart or block diagrams may represent amodule, segment, or portion of code, which comprises at least oneexecutable instruction for implementing the specified logicalfunction(s). It should also be noted that, in some alternativeimplementations, the functions noted in the block may occur out of theorder noted in the figures. For example, two blocks shown in successionmay, in fact, be executed substantially concurrently, or the blocks maysometimes be executed in the reverse order, depending upon thefunctionality involved. It will also be noted that each block of theblock diagrams and/or flowchart illustration, and combinations of blocksin the block diagrams and/or flowchart illustration, can be implementedby special purpose hardware-based systems that perform the specifiedfunctions or acts, or combinations of special purpose hardware andcomputer instructions.

The present invention may be a system, a method, and/or a computerprogram product. The computer program product may include a computerreadable storage medium (or media) having computer readable programinstructions thereon for causing a processor to carry out aspects of thepresent invention.

The computer readable storage medium can be a tangible device that canretain and store instructions for use by an instruction executiondevice. The computer readable storage medium may be, for example, but isnot limited to, an electronic storage device, a magnetic storage device,an optical storage device, an electromagnetic storage device, asemiconductor storage device, or any suitable combination of theforegoing. A non-exhaustive list of more specific examples of thecomputer readable storage medium includes the following: a portablecomputer diskette, a hard disk, a random access memory (RAM), aread-only memory (ROM), an erasable programmable read-only memory (EPROMor Flash memory), a static random access memory (SRAM), a portablecompact disc read-only memory (CD-ROM), a digital versatile disk (DVD),a memory stick, a floppy disk, a mechanically encoded device such aspunch-cards or raised structures in a groove having instructionsrecorded thereon, and any suitable combination of the foregoing. Acomputer readable storage medium, as used herein, is not to be construedas being transitory signals per se, such as radio waves or other freelypropagating electromagnetic waves, electromagnetic waves propagatingthrough a waveguide or other transmission media (e.g., light pulsespassing through a fiber-optic cable), or electrical signals transmittedthrough a wire.

Computer readable program instructions described herein can bedownloaded to respective computing/processing devices from a computerreadable storage medium or to an external computer or external storagedevice via a network, for example, the Internet, a local area network, awide area network and/or a wireless network. The network may comprisecopper transmission cables, optical transmission fibers, wirelesstransmission, routers, firewalls, switches, gateway computers and/oredge servers. A network adapter card or network interface in eachcomputing/processing device receives computer readable programinstructions from the network and forwards the computer readable programinstructions for storage in a computer readable storage medium withinthe respective computing/processing device.

Computer readable program instructions for carrying out operations ofthe present invention may be assembler instructions,instruction-set-architecture (ISA) instructions, machine instructions,machine dependent instructions, microcode, firmware instructions,state-setting data, or either source code or object code written in anycombination of one or more programming languages, including an objectoriented programming language such as Smalltalk, C++ or the like, andconventional procedural programming languages, such as the “C”programming language or similar programming languages. The computerreadable program instructions may execute entirely on the user'scomputer, partly on the user's computer, as a stand-alone softwarepackage, partly on the user's computer and partly on a remote computeror entirely on the remote computer or server. In the latter scenario,the remote computer may be connected to the user's computer through anytype of network, including a local area network (LAN) or a wide areanetwork (WAN), or the connection may be made to an external computer(for example, through the Internet using an Internet Service Provider).In some embodiments, electronic circuitry including, for example,programmable logic circuitry, field-programmable gate arrays (FPGA), orprogrammable logic arrays (PLA) may execute the computer readableprogram instructions by utilizing state information of the computerreadable program instructions to personalize the electronic circuitry,in order to perform aspects of the present invention.

Aspects of the present invention are described herein with reference toflowchart illustrations and/or block diagrams of methods, apparatus(systems), and computer program products according to embodiments of theinvention. It will be understood that each block of the flowchartillustrations and/or block diagrams, and combinations of blocks in theflowchart illustrations and/or block diagrams, can be implemented bycomputer readable program instructions.

These computer readable program instructions may be provided to aprocessor of a general purpose computer, special purpose computer, orother programmable data processing apparatus to produce a machine, suchthat the instructions, which execute via the processor of the computeror other programmable data processing apparatus, create means forimplementing the functions/acts specified in the flowchart and/or blockdiagram block or blocks. These computer readable program instructionsmay also be stored in a computer readable storage medium that can directa computer, a programmable data processing apparatus, and/or otherdevices to function in a particular manner, such that the computerreadable storage medium having instructions stored therein comprises anarticle of manufacture including instructions which implement aspects ofthe function/act specified in the flowchart and/or block diagram blockor blocks.

The computer readable program instructions may also be loaded onto acomputer, other programmable data processing apparatus, or other deviceto cause a series of operational steps to be performed on the computer,other programmable apparatus or other device to produce a computerimplemented process, such that the instructions which execute on thecomputer, other programmable apparatus, or other device implement thefunctions/acts specified in the flowchart and/or block diagram block orblocks.

The flowchart and block diagrams in the Figures illustrate thearchitecture, functionality, and operation of possible implementationsof systems, methods, and computer program products according to variousembodiments of the present invention. In this regard, each block in theflowchart or block diagrams may represent a module, segment, or portionof instructions, which comprises one or more executable instructions forimplementing the specified logical function(s). In some alternativeimplementations, the functions noted in the block may occur out of theorder noted in the figures. For example, two blocks shown in successionmay, in fact, be executed substantially concurrently, or the blocks maysometimes be executed in the reverse order, depending upon thefunctionality involved. It will also be noted that each block of theblock diagrams and/or flowchart illustration, and combinations of blocksin the block diagrams and/or flowchart illustration, can be implementedby special purpose hardware-based systems that perform the specifiedfunctions or acts or carry out combinations of special purpose hardwareand computer instructions.

This disclosure has been presented for purposes of illustration anddescription but is not intended to be exhaustive or limiting. Manymodifications and variations will be apparent to those of ordinary skillin the art. The embodiments were chosen and described in order toexplain principles and practical application, and to enable others ofordinary skill in the art to understand the disclosure.

Although illustrative embodiments of the invention have been describedherein with reference to the accompanying drawings, it is to beunderstood that the embodiments of the invention are not limited tothose precise embodiments, and that various other changes andmodifications may be affected therein by one skilled in the art withoutdeparting from the scope or spirit of the disclosure.

What is claimed is:
 1. A method comprising: identifying, by a viaplacement tool executing on a processor of a circuit design system, aplurality of via groups each comprising a ratio of a plurality of signalvias to one ground via based on a design file defining a layout of amulti-layer circuit board; iteratively evaluating, by a genetic viaplacement solver, a plurality of potential placement solutions thatadjust a placement of one or more of the signal vias until at least onesolution is identified that meets one or more placement criteria of thesignal vias, wherein evaluating the potential placement solutions isperformed with respect to a fitness function that compares back-drilledvia positions with shifts applied according to a shift constraint;performing, by the genetic via placement solver, a mutation andrecombination of one or more solutions that do not meet the one or moreplacement criteria and re-evaluating the one or more solutions that donot meet the one or more placement criteria; modifying the design fileto include at least one shifted signal via position based on identifyingthe at least one solution that meets the one or more placement criteria;and fabricating or having fabricated the multi-layer circuit board basedon the modified design file.
 2. The method of claim 1, wherein thepotential placement solutions comprise a plurality of different radiusvalues and angles to shift one or more of the signal vias.
 3. The methodof claim 1, wherein the one or more placement criteria define a minimumseparation between the signal vias subject to back-drilling.
 4. Themethod of claim 3, wherein the potential placement solutions compriseshifting one or more of the signal vias closer to the ground via in asame group or a different group such that a distance between the atleast one shifted signal via position and the ground via is less thanthe minimum separation between the signal vias subject to back-drilling.5. The method of claim 3, wherein the potential placement solutionscomprise shifting one or more of the signal vias closer to anon-back-drilled signal via such that a distance between the at leastone shifted signal via position and the non-back-drilled signal via isless than the minimum separation between the signal vias subject toback-drilling.
 6. The method of claim 1, further comprising: adding oneor more pad extensions to an uppermost layer of the multi-layer circuitboard to align with bottom surface metal of a module to be coupled tothe multi-layer circuit board, each of the one or more pad extensionsestablishing an electrical connection with one of the signal vias afterthe positioning.
 7. The method of claim 6, wherein an elongated pad iscoupled to the one or more pad extensions to align with bottom surfacemetal of the module.
 8. A method comprising: identifying, by a viaplacement tool executing on a processor of a circuit design system, aplurality of via groups each comprising a ratio of a plurality of signalvias to one ground via based on a design file defining a layout of amulti-layer circuit board; iteratively evaluating, by a genetic viaplacement solver, a plurality of potential placement solutions thatadjust a placement of one or more of the signal vias until at least onesolution is identified that meets one or more placement criteria of thesignal vias, wherein the potential placement solutions comprise aplurality of different radius values and angles to shift one or more ofthe signal vias; performing, by the genetic via placement solver, amutation and recombination of one or more solutions that do not meet theone or more placement criteria and re-evaluating the one or moresolutions that do not meet the one or more placement criteria; modifyingthe design file to include at least one shifted signal via positionbased on identifying the at least one solution that meets the one ormore placement criteria; and fabricating or having fabricated themulti-layer circuit board based on the modified design file.
 9. Themethod of claim 8, wherein the one or more placement criteria define aminimum separation between the signal vias subject to back-drilling. 10.The method of claim 9, wherein the potential placement solutionscomprise shifting one or more of the signal vias closer to the groundvia in a same group or a different group such that a distance betweenthe at least one shifted signal via position and the ground via is lessthan the minimum separation between the signal vias subject toback-drilling.
 11. The method of claim 9, wherein the potentialplacement solutions comprise shifting one or more of the signal viascloser to a non-back-drilled signal via such that a distance between theat least one shifted signal via position and the non-back-drilled signalvia is less than the minimum separation between the signal vias subjectto back-drilling.
 12. The method of claim 8, further comprising: addingone or more pad extensions to an uppermost layer of the multi-layercircuit board to align with bottom surface metal of a module to becoupled to the multi-layer circuit board, each of the one or more padextensions establishing an electrical connection with one of the signalvias after the positioning.
 13. The method of claim 12, wherein anelongated pad is coupled to the one or more pad extensions to align withbottom surface metal of the module.